Time sensitive networking device

ABSTRACT

The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.

TECHNICAL FIELD

The present techniques relate generally to time sensitive networking.More specifically, the present techniques relate to a time sensitivenetworking device that makes use of an enhanced gate control list,sometimes making use of multiple queues, launch times for specificpackets of data, and look-up tables where look-ups are local to thenetworking device.

BACKGROUND ART

Networking devices can receive requests from applications that specificpackets of data be transmitted to another end device on a network. Anetwork interface controller (NIC) is a hardware device that does thetransmission and reception of data to and from an end device on anetwork. Application software that is running on a local system cancreate or uses the data to be transmitted by a networking device such asthe NIC. A NIC that is on the system does the actual transmission andreception of the data. The requests and instructions for transmissionmay not come with an address location for the location of the data onthe local device. Instead a descriptor of the location of the data iscurrently provided by the NIC to the location of the data in main memoryof the local device. Using the descriptor, the networking device mayrequest through a bus and processor an address based on the descriptor.Once the processor returns the address for the data packet, thenetworking device may retrieve and transmit the data packet to the enddevice.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an example network interface system tomanage direct memory access in time sensitive networking ecosystems;

FIG. 2 is a schematic diagram of an example multi-queue using enhancegate control lists;

FIG. 3 is a block diagram of an example queue specific enhanced gatecontrol list;

FIG. 4 is a block diagram illustrating an example computing device fortime sensitive networking;

FIG. 5 is a flow chart illustrating an example method for time sensitivenetworking;

FIG. 6 is a block diagram showing example computer readable media thatstores code for time sensitive networking; and

FIG. 7 is a schematic of an example enhanced gate control list fordynamic memory storage scenarios.

The same numbers are used throughout the disclosure and the figures toreference like components and features. Numbers in the 100 series referto features originally found in FIG. 1 ; numbers in the 200 series referto features originally found in FIG. 2 ; and so on.

DESCRIPTION OF THE EMBODIMENTS

The present disclosure relates to computer networking components thatuse a local look-up table thereby reducing latencies in data retrievaland transfer. In an example, an NIC can implement a local look-up tablecalled an enhanced gate control list. Using the enhanced gate controllist, the NIC scheduler can execute a direct memory access (DMA) of thetarget data directly as well as schedule the data fetches according toqueue traffic class. This scheduling is made possible by the use oflocal look-up tables, but also through the knowledge of the time whendata will be requested, expected by the application using the data. Theability of a NIC, or other computer networking hardware to access datadirectly by having a local look-up table rather than requesting alook-up through a central processor unit (CPU) increases the availableCPU cycles. The local look-up table and the ability to pre-fetch dataand addresses for DMA to execute when expected allow the CPU both morework load consolidation, more determinism, and reduction in end-to-endlatencies. The use of a local look-up table can also be split intomultiple queues within the look-up table where each queue corresponds toa traffic class. Using the multiple traffic class queues allows preciseper packet per traffic class scheduling and improved overall cyclejitter as offsets can be incorporated into transmission scheduling.

The present techniques may make use of time deterministic standards fornetworking hardware. In one example of such standards, the IEEEdeterministic networking referred to collectively as Time SensitiveNetworking (TSN) can provide data transfer scheduling across thenetwork. As a result of the time sensitive nature of these types ofstandards, embedded designs in the industrial and automotive space caninclude TSN controllers.

The present disclosure incorporates an enhanced gate control list(EGCL). The EGCL includes of memory address, size of payload, pre-fetchtime and other control parameters to achieve low latency anddeterminism. An example networking hardware such as a time sensitive NICmaintains EGCL with the ability to serve predetermined memory locations.These memory locations served by the NIC can be directly programmed bythe application one time before beginning of the operation or can beprogrammed periodically per frame.

In an example, once the EGCL is programmed, the NIC can perform directmemory accesses (DMAs) of the data at predetermined time, calledpre-fetch time, before the launch time of the packet. Using DMAs allowsthe payload of the data packet to be directly fetched without goingthrough descriptors or the CPU. This direct retrieval of the data packetusing a DMA reduces end-to-end latency and improves determinism as aresult of the DMA being known and scheduled for a specific packet ofdata.

Using a data look-up table such as the enhanced gate control list at theexample NIC reduces the requests and complexity occurring managed by theapplication software via execution on the CPU. This frees CPU cycles toprocess more data resulting in shorter end-to-end cycle time and morework load consolidation.

In the following disclosure, numerous specific details are set forth,such as examples of specific types of processors and systemconfigurations, specific hardware structures, specific instructiontypes, specific system components, etc. in order to provide a thoroughunderstanding of the present disclosure. It can be apparent, however, toone skilled in the art that these specific details need not be employedto practice the presently disclosed techniques. In other instances, wellknown components or methods, such as specific and alternative processorarchitectures, specific logic circuits/code for described algorithms,specific firmware code, specific interconnect operation, specific logicconfigurations, specific manufacturing techniques and materials,specific compiler implementations, specific expression of algorithms incode, specific power down and gating techniques/logic and other specificoperational details of computer system haven't been described in detailin order to avoid unnecessarily obscuring the presently disclosedtechniques.

The present disclosure also discusses uses of multiple queues locally onthe time sensitive networking equipment, such as the NIC. The use ofmultiple queues enables various traffic classes and distinction betweenexpress packets with high priority and best effort traffic with lowpriority. In an example, express packets can be mapped to a Queue-1 andthe Queue-1 may be mapped to an express traffic class (TC1). The dataflow on TC1 can be routed on a channel of the networking componentcalled Virtual Channel 1 which can be reserved for real-time traffic.The use of virtual local area networks (VLAN) identifiers can enablemapping of VLAN to traffic class (TC) to virtual channel (VC). Thesemappings provide low latency paths for the time sensitive real-timedata. Use of VLAN to map traffic class can further ensure QoS all theway from application to the Ethernet wires, WiFi antenna, or otherinternet communication hardware. Best effort traffic with low prioritycan be mapped to traffic class 0 (TC0) and can be routed on virtualchannel 0 (VC0) which is shared with numerous other input/outputdevices. The best effort traffic is used for non-time-critical trafficand the latencies are not guaranteed.

FIG. 1 is a schematic diagram of an example network interface system 100to manage direct memory access in time sensitive networking ecosystems.The networking interface system 100 can include a networking interfacecontroller (NIC) 102 or other controller that can manage the retrievaland transmission of data at a known time. Within the NIC 102, a gatecontrol list can be initialized by an application. The application canbe requesting transmission of data through the NIC 102 along an outwardfacing data transmission path towards another device such as an Ethernetconnection, a wireless connection, or other connection type. The gatecontrol list governs the timing of events based on the predeterminedschedule provided for each event. By controlling the timing of eventsthat occur the gate control unit can control the data flow through theNIC 102. The scheduler 104 works in coordination with the control gatelist to control data flow according to the schedule determined from thecontrol gate list. To initialize the gate control list in the NIC 102 atest may first be made as to whether or not the NIC 102 is connected andenabled to transmit 106 data outside of the NIC 102 with the gatecontrol list initializing if the connection is confirmed.

The gate control list can include a number of queues. Each queue can bea look-up table 108. Each queue of the gate control list can also beenabled to trigger a direct memory access (DMA). Data retrieved by theNIC 102 in response to a scheduler 104 retrieving data according to thegate control list, the NIC may store this retrieved data fortransmission in a packet buffer 110. In an example there may be aninternal packet buffer 110 for each queue in the gate control list. Inan example, each packet buffer 110 may correspond with the look-up table108 for a particular queue of the control gate list. When the data hasarrived in packet buffer 110, the scheduler 104 may schedule thetransmission of the data in the packet buffer 110. As discussed above,the NIC 102 may transmit 106 data to another device or to a datacommunication channel such as an Ethernet connection.

As disclosed herein, the gate control list may be enhanced to accountfor timing of data retrieval, time data will be used by a requestingapplication, and other time based requests from a device, system, orapplication. Such an enhanced gate control list may have otherenhancements as well. An enhanced gate control list in the NIC mayinclude timing information about the timing data should be madeavailable to the internal packet buffer 110. In an example, the enhancedgate control may provide information to the scheduler to that thescheduler identifies a specific order that the NIC 102 should retrievedata from data buffers. The sequence of data requests may be made from alook-up table 108 or a number of look-up tables based on the informationfor the timing for each requested piece of data. When the scheduler 104determines that a specific data identified in the look-up table 108should be retrieved, that first data can be retrieved from a data buffer1 112.

As this data is retrieved, the data may be held in the packet buffer 110prior to transmission 106. Based on the enhanced gate control list, alook-up table 108 may also provide information to a scheduler indicatingthat the data lists in the look-up table 108 can be retrieved at aparticular time or within a time range. In an example, the second pieceof data retrieved may be from a data buffer 2 114 based on informationprovided in the look-up table regarding timing metrics of the data to berequested. The data packet retrieved from the data buffer 2 114 may beprovided to the packet buffer 110. This process may continue througheach of the listings in the look-up table 108 until data is requestedfrom Data buffer N 116, where N corresponds to the total number ofrequests that a look-up table 108 will make per queue in the enhancedgate control list. The scheduler 104 can start executing from first rowof the queue using the look-up table 108 and progress sequentiallyacross the gate control list until it reaches the last row of the queuevia the look-up table 108.

Additionally, as described with respect to FIG. 2 , the enhanced gatecontrol list may utilize a number of queues each with their own look-uptable 108. The enhanced gate control list may work in concert with thescheduler 104 to identify a sequence and timing during which eachlook-up table will provide the address for data retrieval from a databuffer. In this way, multiple queues can be managed more efficiently toutilize the time data to increase overall throughput speed anddeterminism in a NIC 102.

FIG. 2 is a schematic diagram of an example multi-queue using enhancedgate control lists 200. Like numbered items, such as the scheduler 104,are as described in FIG. 1 .

When the NIC or other transmission device, component, or system makesuse of enhanced gate control list, such a controller may containmultiple queues each embodied through their own look-up table. In anexample, each look-up table has a number of rows each with acorresponding data address that may be requested from data buffers asillustrated in FIG. 1 . The multiple queues for various traffic classesmay also segregate data flow through the scheduler 104 and NIC based ona virtual local area network identification (VLAN ID) or otheridentification. Using the VLAN ID or other identification marker, thequeues can be mapped to various traffic classes based on the priority toprovide quality of service. For example, one queue may include packetsthat are to be delivered in real time, without delay, other queues mayinclude “best effort” packets that can be delayed and are not urgent.The stratification of traffic classes can be extended to match thenumber of queues created within the NIC.

In an example, a scheduler 104 may coordinate the sending of packetsfrom a queue 0 for traffic class 0 202 with an associated enhanced gatecontrol list 0 204. The enhanced gate control list 0 204 may includeinformation about the data packets that are to be retrieved using thequeue 0 for traffic class 0 202. Likewise, the scheduler 104 maycoordinate the sending of packets from a queue 1 for traffic class 1 206with an associated enhanced gate control list 1 208. The enhanced gatecontrol list 1 208 may include information about the data packets thatare to be retrieved using the queue 1 for traffic class 1 206.Similarly, the scheduler 104 may coordinate the sending of packets froma queue 2 for traffic class 2 210 with an associated enhanced gatecontrol list 2 212. The enhanced gate control list 2 212 may includeinformation about the data packets that are to be retrieved using thequeue 2 for traffic class 2 212. This pattern may continue for each ofthe multiple queues enabled for a NIC. In the example shown in FIG. 2 ,the scheduler 104 may coordinate as many as eight queues for eightdifferent data classes as the retrieval of packets for a queue 7 fortraffic class 7 214 is shown with its associated enhanced gate controllist 7 216. The enhanced gate control list 7 216 may include informationabout the data packets that are to be retrieved using the queue 7 fortraffic class 7 214. While the enhanced gate control lists 7 216 areshown separately to provide information about their respective queues,reference to an enhanced gate control list can include all of thevarious enhanced gate control lists used by a scheduler 104collectively. For example, stating the scheduler 104 would make use ofthe enhanced gate control list for multiple queues could include anenhanced gate control list that had a subpart, which the subpart byitself providing information for its particular queue. Accordingly, themultiple enhanced gate control lists shown in FIG. 2 can also be thoughtof collectively as a single enhanced gate control list with manydifferent constituent parts used in managing the data retrieval and flowfrom the various queues.

For each queue, the enhanced gate control list can include at least twoparts for the next row in the queues sequence. A first part of theenhanced gate control list for a queues can include the location of thepacket data. A first part of the enhanced gate control list for a queuescan include the timing details of the packet data to next be retrievedfrom the queue.

In an example, the first part of the enhanced gate control list for aspecific queue can provide a retrieval location for the packet or partof the packet in the main memory and the size of the data. Theselocations may be in main memory or other attached memory depending onthe device in which the scheduler is operating. The enhanced gatecontrol list may obtain this location information from the rows of thequeue the enhanced gate control list serves.

In an example, the second part of the enhanced gate control list for aspecific queue specifies when to fetch the data from memory and when totransmit this packet. These times may be relative to a specific clock inthe NIC or may be a clock signal provided by the scheduler or centralprocessing unit. In an example, each row of the look-up table in thecorresponding queue of the enhanced gate control list contains the timefields for the second part of the enhanced gate control list. In anotherexample, each row of the queues shown in FIG. 2 can have a format andinformation as shown in FIG. 3 to be provided to the enhanced gatecontrol lists.

In one example for FIG. 2 , each row entry in the queue can contain thedirect address location of data in the main memory. By having the directaddress location without having to make a request outside of the NIC102, the scheduler 104 using the enhanced gate control list can do a DMAat a specified time without the dealy of an address request. Theprecision of the time is useful in pre-fetching the data that may nextbe transmitted through the scheduler 104.

In one example, the scheduler 104 begins executing the collective gatecontrol list of each queue, or a single queue if only one queue exists,when the application enables the DMA by writing into DMA enableregister. An internal accumulator, such as the internal packet buffer ofa NIC in concert with the scheduler 104, can be used to add each rowfrom a queue at a desired and scheduled time interval specific to thedata. Data may have a specific time interval based on the requestedquality of service identified for that packet. Data may also have aspecific time interval or schedule based on the application requestingthe data at a specific time or rate. The scheduler 104 in concert with apacket buffer may retrieve the data from a specific row that has beencalled for a specific time while also scheduling the next event.

In one example using a single queue, a scheduler 104 starts executingfrom a first row in the queue and progresses sequentially across thegate control list until it reaches the last row of the queue. Theenhanced gate control list may still provide time intervals andschedules for each of the rows so that if no data is data is requestedduring a given time interval idle packets may instead be transmitted.

In one example using multiple queues, as in FIG. 2 , the scheduler 104identifies the current row entry for each of the multiple queues usingthe information provided by the enhanced gate control list. For example,for queue 0, the enhanced gate control list 0 204 may provide a currentrow for queue 0. For queue 1, the enhanced gate control list 1 208 mayprovide a current row for queue 1. For queue 2, the enhanced gatecontrol list 2 210 may provide a current row for queue 2, and so onwhere for the other queues. A final queue in this example, queue 7 mayprovide a current row for queue 7 through the enhanced gate control list7 216. As the enhanced gate control list for each of these queuesincludes both time and location information about the data packet to beretrieved, the scheduler 104 is able to not only perform a data accessfrom memory for transmission that needs to be transmitted in currenttime, but may also schedule the next data packet to be transmitted.

Using this information, the enhanced gate control list may pre-fetch theaddress information in order to access that data packet through a directmemory. Fetching this address prior to the scheduled transmission of thedata enables a faster and more determinative transmission of data by thescheduler. As used herein, deterministic transmission refers in part tothe reliability and efficiency that is enabled by a system that knowswhat data it will transmit and when the data will be sent. With thisinformation, a receiving system or component can be prepared to receiveand process that information at a specific time rather than waiting forthe packet to be requested, retrieved, and then transmitted. By enablingthe enhanced gate control list to retrieve the direct memory accessaddress information prior to the scheduled transmission time, thescheduler 104 is able to preemptively perform these operations priorinstruction received at the scheduler 104 or NIC.

In another example, queues 0, queue 1, and a scheduler 104 may accountfor pre-fetch and launch time as revealed about the data in the enhancedgate control list of the respective queues. For example, the scheduler104 can sequence events, such as packet retrieval across queues 0 and 1based on the pre-fetch time and launch time. In an example, consider apacket A, B, and C listed in rows of queue-0 have to be transmitted at10 microseconds, 20 microseconds, and 30 microseconds, respectively. Inthis example, consider a packet D listed in a row of queue-1 to betransmitted at 40 microseconds. In this example, the scheduler 104 willread the first row of queue-0 and first row of queue-1 and through theinformation provided by the enhanced gate control list for each queue,determine that packet A from queue-0 needs to be transmitted at 10 usand the size of packet A takes 10 microseconds to transmit. In thisexample, the scheduler 104 checks if the first packet from queue-1,packet D, can be transmitted at 20 microseconds. Since packet D inqueue-1 is scheduled for 40 microseconds, the scheduler 104 reads thenext row of queue-0 to determine if the packet retrieved, packet B, canbe transmitted before the scheduled time for packet D at 40microseconds. Since packet B is scheduled for 20 microseconds with a 10microsecond transmit time, the scheduler 104 knows packet B can bescheduled and transmitted prior to the scheduled time for packet D. Thescheduler 104 will then pre-fetch the data for packet B and willtransmit the packet B.

This process of checking can be repeated for multiple queues using theinformation provided regarding scheduled times and transmit times toefficiently schedule and pre-fetch data packets for transmission. Asnoted above, when data packets can be pre-fetched for transmission theymay be stored in a transmit buffer for transit while the scheduler 104identifies the next packet to retrieve from the queues.

In this example, if the scheduler 104 finds there is no packet among thenumber of queues scheduled to be transmitted between 10 microseconds and40 microseconds, then the scheduler 104 transmits idle packets on thetransmit line of the NIC until the scheduler 104 finds next packet thatcan be transmitted when scheduled. However, by searching each queue forpackets that may be transmitted between the scheduled packettransmission of queue-1 and queue-0, the scheduler 104 using theenhanced gate control list described here avoids sending idle packetentries when other packets can instead be sent. Using the techniquesdescribed for the scheduler 104 using the enhanced gate control list,queues with empty entries that would have been entered on the gatecontrol list for transmission can be avoided and that time can insteadbe filled by a scheduler 104 pre-fetching data from other queues andtransmit these data packets rather than idle packets.

FIG. 3 is a block diagram of an example queue-specific enhanced gatecontrol list 300. The queue-specific enhanced gate control list 300shown here is one example of the information that can be incorporatedinto the systems, components, queues, and schedulers shown in FIG. 1 andFIG. 2 .

The queue-specific enhanced gate control list 300 provides a memoryaddress 302 for a data packet to be retrieved. This data packet addressinformation can come from the row of the queue associated with the queuespecific enhanced gate control list 300. In an example, the memoryaddress 302 can be an address in the main memory of a system. The memoryaddress 302 can be a 64-bit address for the data in the main memory.This address information can be provided to a scheduler in order toperform a DMA for the data at a scheduled time.

The queue-specific enhanced gate control list 300 provides an offsettime 304 to a scheduler. In an example, the offset time may be encodedin 32 bits. As used herein, the offset time is for repeated operations.The scheduler will fetch the data from same address location at fixedintervals without need for enhanced gate control list updates. Forexample, packets to be sent from fixed location at every at an examplerate of once every millisecond, then the scheduler can read thislocation for every millisecond and send the data that is located in thatlocation. This frees up the software scheduling and preparation of theEGCL. The software may dump the new data at that identified location,and the scheduler picks up the dumped data up at a known time. By addingthe offset time 304 to the current launch time of the scheduler, a newlaunch time 306 for a specific packet may be calculated.

The queue-specific enhanced gate control list 300 may include the launchtime 306 measured from the beginning of each frame with the addition ofthe offset time 304. The launch time 306 included in the queue-specificenhanced gate control list 300 can refer to the scheduled launch time306 of a specific data packet listed in a row of a queue. As discussedabove with respect to FIG. 1 and FIG. 2 , the launch time may be used bythe scheduler to determine which packet from which queue should beretrieved or transmitted and when.

The queue-specific enhanced gate control list 300 may also include apre-fetch time 308. As used herein, the pre-fetch time refers to thetime it takes a NIC or a scheduler to fetch the data packet from a databuffer and place it into a transmit buffer. The pre-fetch time 308 canbe used in coordination with the launch time to determine if sufficienttime for pre-fetching exists. In an example, a scheduler compares aqueue's next scheduled packet launch time with the launch time 306 andpre-fetch time 308 of the present queue. Using this comparison, thescheduler can determine if there is sufficient time to pre-fetch andthen launch the data of the queue associated with the queue-specificenhanced gate control list 300. In an example, the pre-fetch time 308can tell the scheduler how soon before the launch of a packet the datacan be fetched or accessed through a DMA. The numerical value of thepre-fetch time 308 can be small for express packets and large for besteffort packets.

The queue-specific enhanced gate control list 300 may include a payloadsize 310. In an example, the payload size can be for a maximum of 2 KB.The payload size may be useful for identifying the appropriate amount ofdata that may be retrieved for a transmit buffer or transmitted within aparticular time frame. For example if the transmit buffer does not havespace for the entire size of the data packet based on the payload size310, then the retrieval and transmission may need to be split andscheduled to accommodate multiple retrievals and transmissions.

In an example, the queue-specific enhanced gate control list 300 mayinclude a status of the packet 312. The status of the packet can be 2bits to indicate the nature of the packet providing the gate controlinformation. In an example, the queue-specific enhanced gate controllist 300 may provide this information in a packet to the scheduler andvarious status and control indications may need to be conveyed about thepacket providing the information of the queue-specific enhanced gatecontrol list 300 to the scheduler. These status and control informationis included in the status of the packet 312.

The queue-specific enhanced gate control list 300 may also include aqueue number 314 for systems where multiple queues are beingimplemented. In the example of FIG. 2 for example, the queue number 314of the queue-specific enhanced gate control list 300 could be one ofeight different queues, i.e. 0-7. In an example, the queue number 314can be indicated with a 3-bit number. In cases where the queue number314 is a 3-bit number, the number of queues can be limited to eightqueues. The scheduler uses the queue number 314 provided in thequeue-specific enhanced gate control list 300 to identify and associatethe information provided with a specific queue so that the scheduler maycompare queues effectively. For example, the process shown in FIG. 2provides an example where the launch and pre-fetch times of packetslisted in various queues was compared between the queues by thescheduler. The scheduler, when requesting information from each queuespecific enhanced gate control list 300 will be able to make thecomparison when it has the specific queue the other data, e.g. launchtime and pre-fetch time, is representing.

All of the information in the queue-specific enhanced gate control list300 may be provided to a scheduler from each of multiple queues eitherone at a time or at the same time depending on the function of thescheduler. The scheduler may use the information obtained from each ofthe queue specific enhanced gate control lists in order to transmit datapackets with current launch times while scheduling packets with laterlaunch times.

FIG. 4 is a block diagram illustrating an example computing device 400for time sensitive networking. The computing device 400 may be, forexample, a laptop computer, desktop computer, tablet computer, mobiledevice, or server, among others. The computing device 400 may include acentral processing unit (CPU) 402 that is configured to execute storedinstructions, as well as a memory device 404 that stores instructionsthat are executable by the CPU 402. The CPU 402 may be coupled to thememory device 404 by a bus 406. Additionally, the CPU 402 can be asingle core processor, a multi-core processor, a computing cluster, orany number of other configurations. Furthermore, the computing device400 may include more than one CPU 402. The memory device 404 can includerandom access memory (RAM), read only memory (ROM), flash memory, or anyother suitable memory systems. For example, the memory device 404 mayinclude dynamic random access memory (DRAM).

The computing device 400 may also include a graphics processing unit(GPU) 408. As shown, the CPU 402 may be coupled through the bus 406 tothe GPU 408. The GPU 408 may be configured to perform any number ofgraphics operations within the computing device 400. For example, theGPU 408 may be configured to render or manipulate graphics images,graphics frames, videos, or the like, to be displayed to a user of thecomputing device 400.

The memory device 404 can include random access memory (RAM), read onlymemory (ROM), flash memory, or any other suitable memory systems. Forexample, the memory device 404 may include dynamic random access memory(DRAM).

The CPU 402 may also be connected through the bus 406 to an input/output(I/O) device interface 410 configured to connect the computing device400 to one or more I/O devices 412. The I/O devices 412 may include, forexample, a keyboard and a pointing device, wherein the pointing devicemay include a touchpad or a touchscreen, among others. The I/O devices412 may be built-in components of the computing device 400, or may bedevices that are externally connected to the computing device 400. Insome examples, the memory device 404 may be communicatively coupled toI/O devices 412 through direct memory access (DMA).

The CPU 402 may also be linked through the bus 406 to a displayinterface 414 configured to connect the computing device 400 to adisplay device 416. The display device 416 may include a display screenthat is a built-in component of the computing device 400. The displaydevice 416 may also include a computer monitor, television, orprojector, among others, that is internal to or externally connected tothe computing device 400.

The computing device also includes a storage device 418. The storagedevice 418 is a physical memory such as a hard drive, an optical drive,a thumbdrive, an array of drives, or any combinations thereof. Thestorage device 418 may also include remote storage drives.

The computing device 400 may also include a network interface controller(NIC) 420. In an example the NIC 420 may be time sensitive. In anexample, time sensitive can refer to the NIC having a time basedreference relative to a data frame being provided or requested by anapplication. The NIC 420 may be configured to connect the computingdevice 400 through the bus 406 to a network 422. The network 422 may bea wide area network (WAN), local area network (LAN), or the Internet,among others. In some examples, the device may communicate with otherdevices through a wireless technology. For example, the device maycommunicate with other devices via a wireless local area networkconnection. In some examples, the device may connect and communicatewith other devices via Bluetooth® or similar technology.

The NIC 420 may also include a scheduler 424, an enhanced gate controllist (EGCL) 426, and a transmitter 428 to enable time sensitivenetworking. In an example, the scheduler 424, EGCL 426, and transmitter428 may all work together to allow local pre-fetching of data packetsfor transmission to a requesting application using direct memoryaccesses that bypass the CPU 402. In an example the EGCL 426 ismaintained on the NIC 420 and includes a direct memory access address, alaunch time, and a pre-fetch time for a data packet.

In an example, the EGCL 426 includes a number of look-up queues, whereeach of the number of look-up queues includes a number of rows in whichdata packet information can be stored for retrieval by the scheduler424. In an example, the number of look-up queues can correspond to adifferent traffic class where each different traffic class has adiffering quality of service. In this example, the scheduler 424 cancompare a front-of-queue data packet in each of the number of look-upqueues and pre-fetches a queue data packet with a scheduled launch timematching the current time of the scheduler 424. The scheduler 424 mayalso compare a front-of-queue data packet in each of the number oflook-up queues and pre-fetches a queue data packet where a sum of thescheduled launch time and transmit time of the queue data packet doesnot conflict with a scheduled launch of a future scheduled data packet.

In an example the transmitter 428 may transmit the data packet retrievedusing the direct memory access address at a launch time identified bythe scheduler. The NIC 420 may be a time-sensitive networking controllerthat includes a packet buffer. In this example, a data packet can betransmitted from the packet buffer for which the data packet wasrequested by the scheduler 424 at the pre-fetch time. The time-sensitivenetworking controller also may apply a virtual local area network labelsto application requested data packets that are then sorted into a numberof queues in maintained by the enhanced gate control logic, wherein thevirtual local area network labels correspond to the traffic class of theapplication requested data packets in each of the number of queues. Inan example, the transmitter 428, EGCL 426, and scheduler 424 are alllocated local to the time-sensitive networking controller such as theNIC 420 and the memory accesses using the direct memory access addressdo not include a query to a CPU 402.

The block diagram of FIG. 4 is not intended to indicate that thecomputing device 400 is to include all of the components shown in FIG. 4. Rather, the computing device 400 can include fewer or additionalcomponents not illustrated in FIG. 4 , such as additional USB devices,additional guest devices, and the like. The computing device 400 mayinclude any number of additional components not shown in FIG. 4 ,depending on the details of the specific implementation. Furthermore,any of the functionalities of the CPU 402 may be partially, or entirely,implemented in hardware and/or in a processor.

FIG. 5 is a flow chart illustrating an example method 500 for timesensitive networking. The example method is generally referred to by thereference number 500 and can be implemented using the system 400 of FIG.5 above.

At block 502, the method includes generating an enhanced gate controllist on a time-sensitive networking controller, the enhanced gatecontrol list comprising a direct memory access address, a launch time,and a pre-fetch time for a data packet. In an example, the EGCL includesa number of look-up queues, where each of the number of look-up queuesincludes a number of rows in which data packet information can be storedfor retrieval by the scheduler. In an example, the number of look-upqueues can correspond to a different traffic class where each differenttraffic class has a differing quality of service. In this example, thescheduler can compare a front-of-queue data packet in each of the numberof look-up queues and pre-fetches a queue data packet with a scheduledlaunch time matching the current time of the scheduler. The schedulermay also compare a front-of-queue data packet in each of the number oflook-up queues and pre-fetches a queue data packet where a sum of thescheduled launch time and transmit time of the queue data packet doesnot conflict with a scheduled launch of a future scheduled data packet.

At block 504, the method includes transmitting, with a transmitter onthe time-sensitive networking controller, the data packet, the datapacket retrieved using the direct memory access address at a launch timeidentified by a scheduler of the time-sensitive networking controller.In an example the transmitter may transmit the data packet retrievedusing the direct memory access (DMA) address at a launch time identifiedby the scheduler. The NIC may be a time-sensitive networking controllerthat includes a packet buffer. In this example, a data packet can betransmitted from the packet buffer for which the data packet wasrequested by the scheduler at the pre-fetch time. The time-sensitivenetworking controller also may apply a virtual local area network labelsto application requested data packets that are then sorted into a numberof queues in maintained by the enhanced gate control logic, wherein thevirtual local area network labels correspond to the traffic class of theapplication requested data packets in each of the number of queues. Inan example, the transmitter, EGCL, and scheduler are all located localto the time-sensitive networking controller such as the NIC and thememory accesses using the DMA address do not include a query to a CPU.

The techniques disclosed in this specification can be executed in asingle device. These techniques may also be accomplished throughinstructions executing on a computing device. These instructions may bepackaged together as a single executable file. The instructions foraccomplishing these disclosed techniques may also be packaged separatelyon a number of devices, packaged separately on a single device, or maybe stored in a non-executable format. Instructions for accomplishing thedisclosed techniques may be encrypted, compressed, or otherwise preparedfor file storage, security, or transport to a variety of computer andnetwork technologies. These instructions may be stored on a singlestorage device or split among several devices including a number ofservers in various geographic locations. In an example, a single manageror controller file may instruct or include instructions for theprovision of the instructions of the disclosed techniques in whole or inpart to a single device or a number of devices. Whether the instructionsexecute through a single device or a number of devices, the instructionsenabling the disclosed capabilities are contemplated as part of thepresent disclosure regardless of how they are stored, transported, orexecuted with regards to the number or location of devices involved inexecution. The pieces of the instructions may be unpacked, configuredfor proper execution, and stored in a first location with theconfiguration instructions located in a second location distinct fromthe first location. The configuration instructions can be initiated byan action, trigger, or instruction that is not co-located in storage orexecution location with the instructions enabling the disclosedtechniques.

FIG. 6 is a block diagram showing example computer readable media 600that stores code for time sensitive networking. The computer readablemedia 600 may be accessed by a processor 602 over a computer bus 604. Asa note, the present disclosure relates to direct memory accesses (DMAs)that bypass at least one processor. Accordingly, while FIG. 6 shows aprocessor 602, another processor may be bypassed by the actions of thescheduler, EGCL, and transmitter in pre-fetching and scheduling, datapackets for transmission. So long as the activity and direct memoryrequests are kept within the controller or processor of a singlecomponent, this can offload the stress or workload of another controllerthat would have otherwise had to field memory access address requests.

Accordingly, the computer readable medium 600 may include codeconfigured to direct the processor 602 to perform the methods describedherein. In some embodiments, the computer readable media 600 may benon-transitory computer readable media. In some examples, the computerreadable media 600 may be storage media. However, in any case, thecomputer readable media do not include transitory media such as carrierwaves, signals, and the like.

The block diagram of FIG. 6 is not intended to indicate that thecomputer readable media 600 is to include all of the components shown inFIG. 6 . Further, the computer readable media 600 may include any numberof additional components not shown in FIG. 6 , depending on the detailsof the specific implementation.

The various software components discussed herein may be stored on one ormore computer readable media 600, as indicated in FIG. 6 . For example,an EGCL generator 606 can generate an enhanced gate control listmaintained on the time-sensitive networking controller, or potentiallyin this case the processor 602. The generated EGCL can include a directmemory access address to the main memory of a system as well as a launchtime and a pre-fetch time for a data packet. The processor 602 canexecute instructions stored in the data packet transmitter 608 totransmit the data packet retrieved using the direct memory accessaddress to the main memory at a launch time identified by the scheduler.

In an example, a time-sensitive networking controller, which in thiscase may be the processor 602 can include a packet buffer. In thisexample, the data packet can be transmitted from the packet buffer forwhich the data packet was requested by the scheduler at the pre-fetchtime. In an example, the enhanced gate control list can include a numberof look-up queues, where each of the number of look-up queues includes anumber of rows in which data packet information can be stored forretrieval by the scheduler. In this example, each of the number oflook-up queues corresponds to a different traffic class where eachdifferent traffic class has a differing quality of service. Thetransmitter, enhanced gate control list, and scheduler are all locatedlocal to the time-sensitive networking controller, in this case theprocessor 602 and the memory accesses using the direct memory accessaddress to the main memory are initiated and completed withoutcommunication between the time-sensitive networking controller, such asthe processor 602 and another distinct processor.

The block diagram of FIG. 6 is not intended to indicate that thecomputer readable media 600 is to include all of the components shown inFIG. 6 . Further, the computer readable media 600 may include any numberof additional components not shown in FIG. 6 , depending on the detailsof the specific implementation.

FIG. 7 is a schematic of an example enhanced gate control list fordynamic memory storage scenarios 700. As used herein, dynamic storagerefers to the data being stored dynamically. Data that is dynamicallystored refers to data that is stored at different locations at differenttimes. The result of data being stored in different places it theaddress of these data locations need to be updated in a gate controllist dynamically as the data locations change. In dynamic memory storagescenarios 700, the address location for data packets may change overtime. The retrieval of a new or changing data location in memory atlaunch time of the data would result in delays or offsets from the timedeterminism the enhanced gate control list accomplished with thescheduler. To account for systems, components, and devices that usedynamic memory, the control of the enhanced gate control list portionsmay change one cycle of time to the next. FIG. 7 shows an enhanced gatecontrol list in both a current cycle 702 and a next cycle 704. In thecurrent cycle 702, the enhanced gate control list has a first portion706 for which the rows of the queue give control, or are owned, by thehardware. In an example, ownership of rows of a queue in the enhancedgate control list allow the hardware, for example a NIC and scheduler toaccess and modify the row information. This access could be to updatethe current location of the data for each of the rows contained inportion 1 706 controlled by the hardware.

The other portion of the enhanced gate control list during the currentcycle 702, is portion 2 708 which would be owned by the softwareapplication. In this context, ownership corresponds to control by thesoftware application that is manipulating or accessing the data packetsstored at the memory locations indicated by the specific rows of theenhanced gate control list in portion 2 708. As the operations of boththe hardware and software could alter the locations of the datacorresponding to the rows of the look-up table portions they control, inthe next cycle 704, ownership of the portions flip. Accordingly, in thenext cycle 704, portion 1 of the enhanced gate control list is owned andaccessed by the software application 710. Also in the next cycle 704,portion 2 of the enhanced gate control list is owned, accessed, andupdated by the hardware 712.

The switching between ownership of these two look-up table portions ofthe enhanced gate control list allows refresh of memory locations whileaccess to the enhanced gate control list is still enabled for theapplication. This cycling can occur between a current cycle 702corresponding to a first frame and next cycle 704 corresponding to anext frame. Accordingly, the ownership of portions of the enhanced gatecontrol list can reset or flip with each frame of data. Using thismodel, while an active look-up table portion of the enhanced gatecontrol list is accessed by the hardware, the second portion of thelook-up table for the enhanced gate control list is accessed by theapplication.

In another embodiment, the portions need not be contiguous or evenlysplit, but may also be a variety of rows in the enhanced gate controllist as identified by the control bits. In an example, the control bitsmay be identified in the status of the packet 312 information of theenhanced gate control list. In an example, the control bits are used toset ownership and the ownership is mutually exclusive between hardwareand software applications. In an example, while the hardware isprocessing on portion of the enhanced gate control list, the secondlook-up table of the enhanced gate control list can be updated by theapplication. In these dynamic memory location systems, the ownership ofthese enhanced gate control lists can switch back and forth repeatedlybetween hardware and application ownership from cycle to cycle toprovide seamless data flow.

EXAMPLES Example 1

In an example, the device for time sensitive networking, including atime-sensitive networking controller, a scheduler of the time-sensitivenetworking controller, an enhanced gate control list maintained on thetime-sensitive networking controller to include a direct memory accessaddress, a launch time, and a pre-fetch time for a data packet, an atransmitter of the time-sensitive networking controller to transmit thedata packet retrieved using the direct memory access address at thelaunch time identified by the scheduler.

The example devices described here may also include where time-sensitivenetworking controller includes a packet buffer; and the data packet istransmitted from the packet buffer for which the data packet wasrequested by the scheduler at the pre-fetch time. The example devicesdescribed here may also include wherein the enhanced gate control listincludes a number of look-up queues, where each of the number of look-upqueues includes a number of rows in which data packet information is bestored for retrieval by the scheduler. The example devices describedhere may also include wherein each of the number of look-up queuescorresponds to a different traffic class where each different trafficclass has a differing quality of service. The example devices describedhere may also include wherein the scheduler compares a front-of-queuedata packet in each of the number of look-up queues and pre-fetches aqueue data packet with a scheduled launch time matching the current timeof the scheduler. The example devices described here may also includewherein the scheduler compares a front-of-queue data packet in each ofthe number of look-up queues and pre-fetches a queue data packet where asum of the scheduled launch time and transmit time of the queue datapacket does not conflict with a scheduled launch of a future scheduleddata packet. The example devices described here may also include thetransmitter of the time-sensitive networking controller is to transmitin a deterministic transmission without making a request through a CPUfor an address of the data packet. The example devices described heremay also include the time-sensitive networking controller is anetworking interface controller. The example devices described here mayalso include the time-sensitive networking controller applies virtuallocal area network labels to application requested data packets that arethen sorted into a number of queues in maintained by the enhanced gatecontrol logic, wherein the virtual local area network labels correspondto the traffic class of the application requested data packets in eachof the number of queues. The example devices described here may alsoinclude the transmitter, enhanced gate control list, and scheduler areall located local to the time-sensitive networking controller and memoryaccesses using the direct memory access address do not include a queryto a CPU.

Example 2

In an example, the method for time-sensitive networking can includegenerating an enhanced gate control list on a time-sensitive networkingcontroller, the enhanced gate control list including a direct memoryaccess address, a launch time, and a pre-fetch time for a data packet,and transmitting, with a transmitter on the time-sensitive networkingcontroller, the data packet, the data packet retrieved using the directmemory access address at the launch time identified by a scheduler ofthe time-sensitive networking controller.

The example methods described here may also include the time-sensitivenetworking controller includes a packet buffer, and the data packet istransmitted from the packet buffer for which the data packet wasrequested by the scheduler at the pre-fetch time. The example methodsdescribed here may also include the enhanced gate control list includesa number of look-up queues, where each of the number of look-up queuesincludes a number of rows in which data packet information is be storedfor retrieval by the scheduler. The example methods described here mayalso include each of the number of look-up queues corresponds to adifferent traffic class where each different traffic class has adiffering quality of service. The example methods described here mayalso include the scheduler compares a front-of-queue data packet in eachof the number of look-up queues and pre-fetches a queue data packet witha scheduled launch time matching the current time of the scheduler.

The example methods described here may also include that the schedulercompares a front-of-queue data packet in each of the number of look-upqueues and pre-fetches a queue data packet where a sum of the scheduledlaunch time and transmit time of the queue data packet does not conflictwith a scheduled launch of a future scheduled data packet. The examplemethods described here may also include the transmitter of thetime-sensitive networking controller is to transmit in a deterministictransmission without making a request through a CPU for an address ofthe data packet. The example methods described here may also include thetime-sensitive networking controller is a networking interfacecontroller. The example methods described here may also include thetime-sensitive networking controller applies virtual local area networklabels to application requested data packets that are then sorted into anumber of queues in maintained by the enhanced gate control logic,wherein the virtual local area network labels correspond to the trafficclass of the application requested data packets in each of the number ofqueues. The example methods described here may also include thetransmitter, enhanced gate control list, and scheduler are all locatedlocal to the time-sensitive networking controller and memory accessesusing the direct memory access address do not include a query to a CPU.

Example 3

In an example, the system for time sensitive networking may include aprocessor, a main memory, a time-sensitive networking controller, ascheduler of the time-sensitive networking controller, an enhanced gatecontrol list maintained on the time-sensitive networking controller toinclude a direct memory access address to the main memory, a launchtime, and a pre-fetch time for a data packet, and a transmitter of thetime-sensitive networking controller to transmit the data packetretrieved using the direct memory access address to the main memory atthe launch time identified by the scheduler.

The example systems described here may also include the time-sensitivenetworking controller includes a packet buffer, and the data packet istransmitted from the packet buffer for which the data packet wasrequested by the scheduler at the pre-fetch time. The example systemsdescribed here may also include the enhanced gate control list includesa number of look-up queues, where each of the number of look-up queuesincludes a number of rows in which data packet information is be storedfor retrieval by the scheduler. The example systems described here mayalso include each of the number of look-up queues corresponds to adifferent traffic class where each different traffic class has adiffering quality of service. The example systems described here mayalso include the transmitter, enhanced gate control list, and schedulerare all located local to the time-sensitive networking controller andmemory accesses using the direct memory access address to the mainmemory are initiated and completed without communication between thetime-sensitive networking controller and the processor.

Example 4

In an example, at least one non-transitory machine-readable mediumhaving instructions stored therein that, in response to being executedon a computing device, causes the computing device to generate anenhanced gate control list on a time-sensitive networking controller,the enhanced gate control list comprising a direct memory accessaddress, a launch time, and a pre-fetch time for a data packet. Theexample machine-readable medium may also transmit, with a transmitter onthe time-sensitive networking controller, the data packet, the datapacket retrieved using the direct memory access address at the launchtime identified by a scheduler of the time-sensitive networkingcontroller.

Example 5

An example apparatus can include a time-sensitive networking controller,a means for scheduling the time-sensitive networking controller, anenhanced gate control list maintained on the time-sensitive networkingcontroller to include a direct memory access address, a launch time, anda pre-fetch time for a data packet, and a means for transmitting thedata packet retrieved using the direct memory access address at thelaunch time identified by the a means for scheduling.

The example apparatus described can also include the time-sensitivenetworking controller comprises a packet buffer, and the data packet istransmitted from the packet buffer for which the data packet wasrequested by the a means for scheduling at the pre-fetch time. Theexample systems described here can also include the enhanced gatecontrol list comprises a plurality of look-up queues, where each of theplurality of look-up queues includes a number of rows in which datapacket information is be stored for retrieval by the a means forscheduling. The example systems described here can also include each ofthe plurality of look-up queues corresponds to a different traffic classwhere each different traffic class has a differing quality of service.The example systems described here can also include the a means forscheduling compares a front-of-queue data packet in each of theplurality of look-up queues and pre-fetches a queue data packet with ascheduled launch time matching the current time of the a means forscheduling.

The example systems described here can also include a means forscheduling compares a front-of-queue data packet in each of theplurality of look-up queues and pre-fetches a queue data packet where asum of the scheduled launch time and transmit time of the queue datapacket does not conflict with a scheduled launch of a future scheduleddata packet. The example systems described here can also include themeans for transmitting of the time-sensitive networking controller is totransmit in a deterministic transmission without making a requestthrough a CPU for an address of the data packet.

The example systems described here can also include the time-sensitivenetworking controller is a networking interface controller. The examplesystems described here can also include the time-sensitive networkingcontroller applies virtual local area network labels to applicationrequested data packets that are then sorted into a plurality of queuesin maintained by the enhanced gate control logic, wherein the virtuallocal area network labels correspond to the traffic class of theapplication requested data packets in each of the plurality of queues.The example systems described here can also include the means fortransmitting, enhanced gate control list, and a means for scheduling areall located local to the time-sensitive networking controller and memoryaccesses using the direct memory access address do not include a queryto a CPU.

While the present techniques have been described with respect to alimited number of embodiments, those skilled in the art can appreciatenumerous modifications and variations therefrom. It is intended that theappended claims cover all such modifications and variations as fallwithin the true spirit and scope of this present techniques.

A module as used herein refers to any combination of hardware, software,and/or firmware. As an example, a module includes hardware, such as amicro-controller, associated with a non-transitory medium to store codeadapted to be executed by the micro-controller. Therefore, reference toa module, in one embodiment, refers to the hardware, which isspecifically configured to recognize and/or execute the code to be heldon a non-transitory medium. Furthermore, in another embodiment, use of amodule refers to the non-transitory medium including the code, which isspecifically adapted to be executed by the microcontroller to performpredetermined operations. In yet another embodiment, the term module (inthis example) may refer to the combination of the microcontroller andthe non-transitory medium. Often module boundaries that are illustratedas separate commonly vary and potentially overlap. For example, a firstand a second module may share hardware, software, firmware, or acombination thereof, while potentially retaining some independenthardware, software, or firmware. In one embodiment, use of the termlogic includes hardware, such as transistors, registers, or otherhardware, such as programmable logic devices.

The embodiments of methods, hardware, software, firmware or code setforth above may be implemented via instructions or code stored on amachine-accessible, machine readable, computer accessible, or computerreadable medium which are executable by a processing element. Anon-transitory machine-accessible/readable medium includes any mechanismthat provides (i.e., stores and/or transmits) information in a formreadable by a machine, such as a computer or electronic system. Forexample, a non-transitory machine-accessible medium includesrandom-access memory (RAM), such as static RAM (SRAM) or dynamic RAM(DRAM); ROM; magnetic or optical storage medium; flash memory devices;electrical storage devices; optical storage devices; acoustical storagedevices; other form of storage devices for holding information receivedfrom transitory (propagated) signals (e.g., carrier waves, infraredsignals, digital signals); etc., which are to be distinguished from thenon-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of the presenttechniques may be stored within a memory in the system, such as DRAM,cache, flash memory, or other storage. Furthermore, the instructions canbe distributed via a network or by way of other computer readable media.Thus a machine-readable medium may include any mechanism for storing ortransmitting information in a form readable by a machine (e.g., acomputer), but is not limited to, floppy diskettes, optical disks,Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks,Read-Only Memory (ROMs), Random Access Memory (RAM), ErasableProgrammable Read-Only Memory (EPROM), Electrically ErasableProgrammable Read-Only Memory (EEPROM), magnetic or optical cards, flashmemory, or a tangible, machine-readable storage used in the transmissionof information over the Internet via electrical, optical, acoustical orother forms of propagated signals (e.g., carrier waves, infraredsignals, digital signals, etc.). Accordingly, the computer-readablemedium includes any type of tangible machine-readable medium suitablefor storing or transmitting electronic instructions or information in aform readable by a machine (e.g., a computer).

In the foregoing specification, a detailed description has been givenwith reference to specific embodiments. It may be evident that variousmodifications and changes may be made thereto without departing from thebroader spirit and scope of the present techniques as set forth in theappended claims. The specification and drawings are, accordingly, to beregarded in an illustrative sense rather than a restrictive sense.Furthermore, the foregoing use of embodiment and other language does notnecessarily refer to the same embodiment or the same example, but mayrefer to different and distinct embodiments, as well as potentially thesame embodiment.

What is claimed is:
 1. A network interface device, comprising: ascheduler to access an enhanced gate control list, where the enhancedgate control list includes a direct memory access address and a launchtime for a data packet; and a transmitter to transmit, at the launchtime identified by the scheduler, the data packet retrieved from memoryusing the direct memory access address.
 2. The network interface deviceof claim 1, wherein the enhanced gate control list includes a pre-fetchtime for the data packet; and wherein the network interface devicecomprises a packet buffer, wherein the data packet was requested by thescheduler at the pre-fetch time, to be stored in the packet buffer, andis transmitted from the packet buffer.
 3. The network interface deviceof claim 2, wherein the scheduler compares a front-of-queue data packetin each of a plurality of look-up queues and pre-fetches a queue datapacket with a scheduled launch time matching a current time of thescheduler.
 4. The network interface device of claim 1, wherein theenhanced gate control list comprises a plurality of look-up queues,where each of the plurality of look-up queues includes a number of rowsin which data packet information is be stored for retrieval by thescheduler.
 5. The network interface device of claim 4, wherein each ofthe plurality of look-up queues corresponds to a different traffic classwhere each different traffic class has a differing quality of service.6. The network interface device of claim 4, wherein the schedulercompares a front-of-queue data packet in each of the plurality oflook-up queues and pre-fetches a queue data packet, where a sum of ascheduled launch time and a transmit time of the queue data packet doesnot conflict with a scheduled launch of a future scheduled data packet.7. The network interface device of claim 1, wherein the transmitter ofthe network interface device is to transmit in a deterministictransmission without making a request through a central processing unit(CPU) for an address of the data packet.
 8. The network interface deviceof claim 1, wherein the network interface device applies virtual localarea network labels to application requested data packets that are thensorted into a plurality of queues in maintained by the enhanced gatecontrol list, wherein the virtual local area network labels correspondto a traffic class of the application requested data packets in each ofthe plurality of queues.
 9. The network interface device of claim 1,wherein memory accesses by the transmitter, enhanced gate control list,and scheduler use the direct memory access address that do not include aquery to a central processing unit (CPU).
 10. The network interfacedevice of claim 1, wherein the enhanced gate control list includescontrol bits, the control bits used to set ownership by either hardwareor software.
 11. The network interface device of claim 10, wherein theenhanced gate control list is processed alternatively by hardware orsoftware from cycle to cycle to provide seamless data flow.
 12. Acompute node in a network, the compute node comprising: a processor; amemory device; and a network interface card, wherein the networkinterface card includes: a scheduler to: access an enhanced gate controllist, where the enhanced gate control list includes a direct memoryaccess address in the memory device, a launch time, and a pre-fetch timefor a data packet; and copy the data packet from the direct memoryaccess address to a packet buffer without querying the processor, at thepre-fetch time; and a transmitter to transmit the data packet from thepacket buffer at the launch time.
 13. The compute node of claim 12,wherein the enhanced gate control list comprises a plurality of look-upqueues, where each of the plurality of look-up queues includes a numberof rows in which data packet information is be stored for retrieval bythe scheduler.
 14. The compute node of claim 13, wherein each of theplurality of look-up queues corresponds to a different traffic classwhere each different traffic class has a differing quality of service.15. The compute node of claim 14, wherein the scheduler compares afront-of-queue data packet in each of the plurality of look-up queuesand pre-fetches a queue data packet, where a sum of a scheduled launchtime and a transmit time of the queue data packet does not conflict witha scheduled launch of a future scheduled data packet.
 16. A method,comprising: accessing, by a scheduler, an enhanced gate control list,where the enhanced gate control list includes a direct memory accessaddress and a launch time for a data packet; and transmitting, at thelaunch time identified by the scheduler, the data packet retrieved frommemory using the direct memory access address.
 17. The method of claim16, wherein the enhanced gate control list includes a pre-fetch time forthe data packet; and wherein the method comprises: requesting, at thepre-fetch time, the data packet, which is stored in a packet buffer, andis transmitted from the packet buffer.
 18. The method of claim 17,comprising comparing a front-of-queue data packet in each of a pluralityof look-up queues and pre-fetches a queue data packet with a scheduledlaunch time matching a current time of the scheduler.
 19. The method ofclaim 16, wherein the enhanced gate control list comprises a pluralityof look-up queues, where each of the plurality of look-up queuesincludes a number of rows in which data packet information is be storedfor retrieval by the scheduler.
 20. The method of claim 19, wherein eachof the plurality of look-up queues corresponds to a different trafficclass where each different traffic class has a differing quality ofservice.
 21. The method of claim 19, comprising comparing afront-of-queue data packet in each of the plurality of look-up queuesand pre-fetches a queue data packet, where a sum of a scheduled launchtime and a transmit time of the queue data packet does not conflict witha scheduled launch of a future scheduled data packet.
 22. The method ofclaim 16, comprising applying virtual local area network labels toapplication requested data packets that are then sorted into a pluralityof queues in maintained by the enhanced gate control list, wherein thevirtual local area network labels correspond to a traffic class of theapplication requested data packets in each of the plurality of queues.23. At least one non-transitory machine-readable medium includinginstructions, which when executed by a time-sensitive network interfacecontroller, cause the time-sensitive network interface controller toperform operations comprising: accessing, by a scheduler, an enhancedgate control list, where the enhanced gate control list includes adirect memory access address and a launch time for a data packet; andtransmitting, at the launch time identified by the scheduler, the datapacket retrieved from memory using the direct memory access address. 24.The at least one non-transitory machine-readable medium of claim 23,wherein the enhanced gate control list includes a pre-fetch time for thedata packet; and wherein the operations comprise: requesting, at thepre-fetch time, the data packet, which is stored in the packet buffer,and is transmitted from the packet buffer.
 25. The at least onenon-transitory machine-readable medium of claim 24, comprisingoperations of comparing a front-of-queue data packet in each of aplurality of look-up queues and pre-fetches a queue data packet with ascheduled launch time matching a current time of the scheduler.
 26. Theat least one non-transitory machine-readable medium of claim 23, whereinthe enhanced gate control list comprises a plurality of look-up queues,where each of the plurality of look-up queues includes a number of rowsin which data packet information is be stored for retrieval by thescheduler.
 27. The at least one non-transitory machine-readable mediumof claim 26, wherein each of the plurality of look-up queues correspondsto a different traffic class where each different traffic class has adiffering quality of service.
 28. The at least one non-transitorymachine-readable medium of claim 26, comprising operations of comparinga front-of-queue data packet in each of the plurality of look-up queuesand pre-fetches a queue data packet, where a sum of a scheduled launchtime and a transmit time of the queue data packet does not conflict witha scheduled launch of a future scheduled data packet.
 29. The at leastone non-transitory machine-readable medium of claim 23, comprisingoperations of applying virtual local area network labels to applicationrequested data packets that are then sorted into a plurality of queuesin maintained by the enhanced gate control list, wherein the virtuallocal area network labels correspond to a traffic class of theapplication requested data packets in each of the plurality of queues.